The present technique relates to an apparatus and method for managing a branch information storage referred to by fetch circuitry when fetching instructions for processing by a processor.
Within a data processing apparatus, fetch circuitry can be employed to fetch instructions from memory for execution by an associated processor pipeline. To improve the overall performance, it is useful for the fetch circuitry to detect at an early stage instructions that are branch instructions, as information about such branch instructions can be used to influence which subsequent instructions to fetch from memory.
To assist the fetch circuitry in detecting the presence of branch instructions, it is known to provide branch information storage in association with the fetch circuitry, which contains a plurality of entries, where each entry identifies an address indication for a branch instruction, along with associated branch information about that branch instruction. The branch information can take a variety of forms, but may for example identify a target address for the branch instruction.
The branch information storage is an expensive resource with a finite number of entries, and accordingly it would be desirable to provide a mechanism for making more efficient use of the available entries within the branch information storage.